1. Field of the Invention
The present invention relates generally to processes for fabricating integrated circuits and semiconductor devices, and more particularly to a method of patterning elements in a semiconductor topography and a semiconductor device formed thereby.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
A pervasive trend in modern integrated circuit manufacture is to produce integrated circuits (IC) with feature sizes as small as possible. Smaller feature sizes may allow more IC elements to be placed on a single substrate. In addition, ICs with smaller feature sizes may function faster and/or at lower threshold voltages than ICs having larger feature sizes. For example, the continuous scaling of very large scale integrated circuit (VLSI) technologies has required dimensions of gates in some field effect transistor (FET) technologies to shrink to less than approximately 100 nanometers (nm) in order to provide desired FET performance. IC feature sizes, however, may be limited by the image resolution or, more specifically, the wavelength of the photolithographic equipment used to form the features. For example, the minimum resolvable feature size of a 248 nm photolithographic tool may be approximately 0.14 microns. As such, in order to obtain a structure with a smaller feature size, a smaller wavelength photolithographic tool may need to be used.
There are, however, disadvantages with using smaller wavelength photolithographic tools. In particular, photolithographic tools are typically expensive and therefore, purchasing new photolithographic tools for each new development of ICs with reduced feature sizes may be cost prohibitive. Furthermore, smaller wavelength photolithographic tools may require substantial process development to produce smaller feature sizes. In addition, the thicknesses and materials used for photoresist films and underlying anti-reflective layers may be dependent on the wavelength used with the photolithographic tool and therefore, may need to be revised for consistency with the new photolithographic tools. In some cases, problems, such as poor image resolution, poor etch selectivity, or patterning clarity such as line edge roughness, may arise with such immature technologies and chemistries. As a result, the installation of new photolithographic equipment and its associated chemistry may delay the development of integrated circuits with reduced feature sizes. Furthermore, the wavelength of light presently used for lithography is already in the deep ultraviolet range and at such wavelengths the absorption of light by components in the lithography tool is considerable. Thus, it may not be possible to produce circuit elements having dimensions of 100 nm or less by simply reducing the wavelength lithography light source.
One method of producing IC elements with dimensions smaller than dimensions obtainable by a photolithographic tool is “resist trimming.” In resist trimming, a resist is first patterned to a dimension within the capability limit of the lithography tool. The pattern is then trimmed in an etch tool to a narrower, desired dimension, and the semiconductor topography is etched using the trimmed resist pattern. Although an improvement over conventional lithographic techniques, the resist trimming approach is not wholly satisfactory for a number of reasons. For instance, dimension uniformity among a plurality of patterned elements is significantly degraded by the resist trimming, thereby reducing the utility of this approach for mass commercial production of ICs having dimensions below the resolution of the lithography tool. Moreover, resist trimming typically reduces both width and length dimensions of a structure. Consequently, although it may be advantageous to reduce one dimension of a structure, such as width for example, the other dimension of the structure will also be reduced, possibly beyond the design specifications of the structure. In addition, resist trimming may undesirably increase spacing distances between structures, sometimes out of the design specifications of the device.
Accordingly, there is a need for a method of patterning or defining elements within a semiconductor topography that is not limited by the capabilities of lithographic tools or processes. It is further desirable that the method provide elements having smaller and/or more uniform dimensions than those that may be achieved by advanced lithographic tools and/or resist trimming processes. Moreover, it would be advantageous to develop a method patterning elements within a semiconductor topography a lower cost than such processes.